1. Field of the Invention
The present invention relates to a non-volatile memory device, and more particularly to a reference potential generation technology in the read operation of a 1T1C type ferroelectric memory FeRAM (Ferroelectric Random Access Memory).
2. Description of the Related Art
FIG. 11 shows the configuration of a conventional 1T1C (one transistor one capacitor) type ferroelectric memory. This shows a memory cell array with a 1 row, 2 n column, 1 I/O configuration, where n can be an arbitrary integer.
1001 to 1008 are 1T1C type ferroelectric memory cells. 1011 to 1014 are sense amplifiers for amplifying the potential difference of the bit lines BLt [2n+1:0] and BLb [2n+1:0] which are in a complementary relationship. Cb is a parasitic capacitance of the bit line. 1021 to 1024 are reference cells for generating reference potential. 1031 is a reference potential regulator for adjusting the reference potential.
BLt [2n+1:0] indicates all of BLt [0], BLt [1] to BLt [2n+1], and BLb [2n+1:0] indicates all of BLb [0], BLb [1] to BLb [2n+1]. Of these, the bit lines BLt [0] and BLb [0], bit lines BLt [1] and BLb [1], bit lines BLt [2n+l] and BLb [2n+1] are in a complementary relationship respectively.
WL is a select signal for selectively connecting the first terminal of the ferroelectric capacitor in the 1T1C type ferroelectric memory cell to the bit line.
CP is a cell plate line for applying the power supply voltage or the ground potential to the second terminals of the ferroelectric capacitors in the 1T1C type ferroelectric memory cells.
REFWL is a select signal for connecting the first terminal of the ferroelectric capacitor of the reference cell to the bit line.
REFCP is a reference cell plate line for applying the power supply voltage or the ground potential to the second terminals of the ferroelectric capacitors of the reference cells.
REFEQ is a control signal for conducting the equalization transistor for equalizing the potential of the bit lines.
EQN is a node for connecting bit lines.
REFST is a select signal for applying a predetermined voltage on the ferroelectric capacitors of the reference cells.
REFSET is a reference cell write line for applying the power supply voltage or the ground potential to the ferroelectric capacitors of the reference cells.
FE_tb [m:0] is a ferroelectric capacitor for storing electric charges for adjusting the reference potential.
EQLEVEL is a potential for storing the electric charges in FE_tb [m:0] for adjusting the reference potential.
EQSET is a control signal for storing the electric charges in FE_tb [m:0].
EQADJUST is a control signal for releasing the electric charges stored in FE_tb [m:0] and adjusting the reference potential by connecting EQNA and EQN.
FIG. 12 shows a timing chart of this prior art.
At the timing t1, WL and REFWL become VPP level (power supply voltage VDD+“NMOS Vt”), and the first terminals of the ferroelectric capacitors of the ferroelectric memory cells are connected to BLt [2n+1:0] respectively, and the first terminals of the ferroelectric capacitors of the reference cells are also connected to the BLb [2n+1:0] respectively.
At the timing t2, CP and REFCP become VDD level (power supply voltage level), and at timing t3, CP and REFCP become ground level, so that the ferroelectric memory cells are read to the BLt [2n+1:0] (for details on the read principle, see Japanese Patent Application Laid-Open No. H8-115596), and data written to the reference cells is read to the BLb [2n+1:0].
At the timing t4, all the BLb [2n+1:0] of the BLb [2n+1:0] are equalized. In the ferroelectric capacitors FE_b [n:0] of the reference cells, the data “1” has been written in advance, and in FE_t [n:0], the data “0” has been written in advance. By this equalization, the potential of BLb [2n+1:0] becomes the reference potential. If the potential of the data “1”, which is read to the BLt [2n+1:0], is vH and the potential of the data “0” is vL, the reference potential Vref_e at this equalization becomesVref—e=(vH+vL)/2.
At the timing t4a, EQN and EQNA are connected. In this case, FEFL and EQLEVEL are at ground level, so electric charges are redistributed according to the capacity of FE_tb [m:0] connected to EQNA, and the potential of EQN drops. This operation is the adjustment operation of the reference potential Vref.
At the timing t5, EQADJUST becomes ground level, and the adjustment operation of the reference potential ends.
At the timing t6, the sense amplifiers are activated, and the amplification operation of BLt [2n+1:0] and the reference potential BLb [2n+1:0] is performed.
At the timing t7, the ferroelectric capacitors of the reference cells are disconnected from BLb [2n+1:0].
At the timing t8, the precharge of the reference potential adjustment node EQNA starts and REFST becomes VPP level, and at the timing t9, the writing of the data “0” to FE_t [n:0] of the reference cell starts.
At the timing t10, CP becomes VDD level, and the data “0” of the 1T1C type ferroelectric memory cells is written, and at the timing t11, the rewriting of the data “0” ends.
At the timing t12, WL becomes ground level, and the ferroelectric capacitors of the 1T1C memory cells are disconnected from BLt [2n+1:0].
At the timing t13, REFSET becomes ground level, the writing of the data “0” to the ferroelectric capacitors FE_t [n:0] of the reference cells ends, REFST becomes ground level, the first terminals of the reference cells FE_t [n:0] are disconnected from REFSET, and the first terminals of FE_b [n:0] are disconnected from ground.
At the timing t15, the bit lines BLt [2n+1:0] and BLb [2n+1:0] are discharged to the ground level, and the read operation completes (e.g. Japanese Patent Application Laid-Open No. H8-115596, see page 12, FIG. 16).
However, in a conventional method, the reference potential Vref is the intermediate potential of the data “1” and the data “0”, which is output to the bit lines read from the 1T1C type ferroelectric memory cells. And for the adjustment, either adding or subtracting a predetermined voltage ΔVref alone is possible. In other words, according to a conventional method, the reference potential isVrefH=Vref+ΔVref VrefM=Vref VrefL=Vref−ΔVref, that is, there is a limit of three values at the intermediate potential of the data “1” and the data “0” which are output to the bit lines read from the Vref:1T1C type ferroelectric memory cells. With this, fine adjustment of the reference potential, which is most important in 1T1C operation, cannot be performed, and improving yield is difficult. Also the dispersion of reference potential after retention is large, so the ferroelectric memory has a retention problem.